1. Field of the Invention
This invention relates generally to the art of in-circuit testing of RAMs. More specifically, the invention relates to scanpath testing of RAMs embedded on VLSI chips.
2. Related Art
The dense integration (VLSI) of logic on a single silicon microchip has created immense problems for the test engineer. In order manage functional testing of such complex circuitry, the VLSI chip must be divided into independently testable blocks. A RAM is one such block.
Although the structure of the RAM is simple, it is difficult to test because it is sequential, each address is uniquely addressable, and the RAM is susceptible to a variety of fault conditions, each requiring a unique test. In the past, three approaches have been used to test these embedded RAMs. Each has significant advantages and disadvantages.
Small embedded RAMs can be tested using normal scanpath testing. Scanpath testing involves interfacing the chip with a RAM tester, and then serially shifting an address, data, and control information into and out of the chip for each RAM address to be tested. Each address requires a shift in, shift out operation.
This conventional scanpath approach is straightforward and very flexible. Test patterns are easily changed in the tester prior to being shifted into the RAM, and when unexpected failure mechanisms are discovered, the scanpath can be used to access specific RAM addresses such that special tests can be performed to provide detailed diagnostics. Also, a minimal amount of additional chip hardware is required if a scanpath and diagnostic interface port (DIP) are already resident on the chip.
The main disadvantage of normal scanpath testing is that it is time intensive due to the fact that each address requires a shift in, shift out operation, and each shift in, shift out operation may require several hundred clock cycles. For large embedded RAMs, this can make testing painfully slow.
Another disadvantage of normal scanpath testing is that it is impossible to read or write to a sequence of addresses at full speed, since a new address, possibly new write data, and new control bits must be serially shifted (i.e., scanned) in for each address.
A second test approach for the embedded RAM is to make all RAM signals (i.e., all address lines and data lines) available at the pads of the microchip. This allows the tester to have complete and direct control over the RAM.
While this is ideal from a test standpoint, making all RAM signals externally accessible requires additional signal routing to bring the signals to the periphery of the chip. In addition, multiplexing circuitry is often required such that pads may be shared. A significant increase in chip area results from the additional hardware.
A further disadvantage of directly testing in this manner is that the test equipment must directly create all test patterns. This requires a special test pattern generator or a tester with a very large amount of vector memory.
A third test approach is the self-test. Conventional (hardware-based) self-tests generally use a dedicated controller (i.e., a dedicated state machine such as a programmable logic array) and a data pattern generator which together generate test patterns and then cycle the RAM through a predefined sequence of operations. Such a test has the advantage that it can be run at full speed with a minimum of special hardware or software in the tester.
An example of a convention RAM self-test circuit is given in R. Dekker, et al., "Realistic Built-in Self-test for Embedded RAMs," IEEE Design & Test of Computers, 1989, pages 26-34, (IEEE order no. 0740-7475/89/0002-26$1.00).
The self-test suffers from the disadvantage that a large amount of on-chip hardware may be required to create the dedicated controller and the data pattern generator. Further, conventional self-tests provide only pass/fail results such that it may not be possible to obtain more detailed diagnostics. In addition, since the test sequence is fixed in hardware, the sequence cannot be modified without modifying the chip. This inflexibility poses a significant problem when unexpected failure mechanisms, which require new tests, are discovered after manufacture of the chip.
A further shortcoming of self-test is that the dedicated controller normally supplies its control signals to the RAM over a distinct control path such that the regular control path is not tested.
It is an object of the present invention to overcome the deficiencies of these known test methods by providing a flexible, efficient test system and method that can be run at full speed, will provide detailed diagnostics, and will fully test an embedded RAM.